完整後設資料紀錄
DC 欄位語言
dc.contributor.authorHuang, Shih-Enen_US
dc.contributor.authorYu, Chien-Linen_US
dc.contributor.authorSu, Pinen_US
dc.date.accessioned2019-08-02T02:18:32Z-
dc.date.available2019-08-02T02:18:32Z-
dc.date.issued2019-06-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2019.2907994en_US
dc.identifier.urihttp://hdl.handle.net/11536/152342-
dc.description.abstractThis paper investigates the fin-width (W-Fin) sensitivity of threshold voltage (V-T) for InGaAs and Si channel negative-capacitance FinFETs (NC-FinFETs) using a theoretically derived quantum subthreshold model corroborated with TCAD numerical simulation. Our study indicates that due to the action of negative capacitance, the NC-FinFET possesses smaller VT sensitivity to W-Fin than the FinFET counterpart. In addition, we point out and demonstrate that a device design with higher internal voltage amplification can be utilized to further reduce the V-T sensitivity to W-Fin for NC-FinFETs. Our study may provide insights for future scaling of FinFETs.en_US
dc.language.isoen_USen_US
dc.subjectCMOSen_US
dc.subjectFinFETen_US
dc.subjectInGaAsen_US
dc.subjectnegative-capacitance field-effect transistor (NCFET)en_US
dc.subjectquantum confinement (QC)en_US
dc.titleInvestigation of Fin-Width Sensitivity of Threshold Voltage for InGaAs and Si Negative-Capacitance FinFETs Considering Quantum-Confinement Effecten_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2019.2907994en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume66en_US
dc.citation.issue6en_US
dc.citation.spage2538en_US
dc.citation.epage2543en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000468228100011en_US
dc.citation.woscount0en_US
顯示於類別:期刊論文