標題: Evaluation of an InAs HEMT with source-connected field plate for high-speed and low-power logic applications
作者: Yao, Jing Neng
Lin, Yueh Chin
Lin, Min Song
Huang, Ting Jui
Hsu, Heng Tung
Sze, Simon M.
Chang, Edward Y.
材料科學與工程學系
電子工程學系及電子研究所
國際半導體學院
Department of Materials Science and Engineering
Department of Electronics Engineering and Institute of Electronics
International College of Semiconductor Technology
關鍵字: InAs;Field plate;Low power;HEMT
公開日期: 1-Jul-2019
摘要: In this study, we have presented a source-connected field plate (SCFP) InAs high electron mobility transistor (HEMT) and evaluated its potential for using in high-speed and low-power logic applications. The fabricated device demonstrated good electrical characteristics including low subthreshold swing (SS) of 76 mV/decade, drain induced barrier lowering (DIBL) of 44 mV/V, I-ON/I-OFF ratio of 2.4x10(4), an off-state gate leakage current of less than 5x10(-6) A/mm and a G(m,max) of 1100 mS/mm at V-DS = 0.5 V. When increasing the drain-source bias (V-DS) to 1.0 V, the G(m,max) increased to 1750 mS/mm with a cut-off frequency of 113 GHz. These results revealed that the fabrication of source-connected field plate InAs HEMTs achieved excellent device performance for high-speed and low-power logic applications.
URI: http://dx.doi.org/10.1016/j.sse.2019.03.060
http://hdl.handle.net/11536/152401
ISSN: 0038-1101
DOI: 10.1016/j.sse.2019.03.060
期刊: SOLID-STATE ELECTRONICS
Volume: 157
起始頁: 55
結束頁: 60
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