Investigation of Degradation Phenomena in GaN-on-Si Power MIS-HEMTs under Source Current and Drain Bias Stresses

Abstract

In this paper, we investigate the degradation phenomena in GaN-on-Si Metal-Insulator-Semiconductor High electron Mobility Transistors (MIS-HEMTs) in the cascode topography for enhancement mode power switching applications. Different stress conditions, e.g., constant source current (Is=100(mu A)=2(mA/mm) and 100(nA)=2 x 10(-3)(mA/mm)) and drain voltages (V-D=1(V), 10(V), 100(V), and 200(V)), are used to investigate the source current and drain bias dependent degradation. First, the VTH shift is correlated with the RoN increase under a low drain bias stress (V-D<10(V)). However, under a high drain bias stress, the trapping location is most probably in the gate-to-drain access region, leading a different degradation phenomena compared to the case under a low drain bias stress. Furthermore, we found that the devices are stressed under a different source current stress show a similar degradation phenomenon. This suggests that, in the cascode circuit topology, the instability degradation is still mainly triggered by the drain bias.