標題: | Package and Chip Accelerated Aging Methods for Power MOSFET Reliability Evaluation |
作者: | Lin, Tingyou Su, Chauchin Hung, Chung-Chih Nidhi, Karuna Tu, Chily Huang, Shao-Chang 交大名義發表 電信工程研究所 National Chiao Tung University Institute of Communications Engineering |
關鍵字: | accelerated aging;accelerated testing;power MOSFET |
公開日期: | 1-一月-2019 |
摘要: | This paper investigates power MOSFET stress strategies for both package and chip aging evaluation. Two stress test methods are developed to speed up packaging and chip aging process respectively. As a result, the characteristics shifts of package and chip aging can be plotted independently. Thus, the measurement accuracy and measurement time can be improved. A test chip is designed and fabricated in a 0.15tm BCD process. The measured results demonstrate a 10kjtm power MOSFET has R-on increased by 72% after 6.3hr stress for the package aging. For the chip aging, the MOSFET has R-on increased by 12% after 600 times stress pulses. The measurement verifies that the accelerated aging in the package and the chip can be controlled separately. |
URI: | http://hdl.handle.net/11536/152480 |
ISBN: | 978-3-9819263-2-3 |
ISSN: | 1530-1591 |
期刊: | 2019 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE) |
起始頁: | 1661 |
結束頁: | 1666 |
顯示於類別: | 會議論文 |