完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wang, Yu-Zhe | en_US |
dc.contributor.author | Wu, Jingjie | en_US |
dc.contributor.author | Chen, Shi-Hao | en_US |
dc.contributor.author | Chao, Mango Chia-Tso | en_US |
dc.contributor.author | Yang, Chia-Hsiang | en_US |
dc.date.accessioned | 2019-09-02T07:45:41Z | - |
dc.date.available | 2019-09-02T07:45:41Z | - |
dc.date.issued | 2019-01-01 | en_US |
dc.identifier.isbn | 978-1-7281-0655-7 | en_US |
dc.identifier.issn | 2474-2724 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/152561 | - |
dc.description.abstract | Cryptocurrencies have recently gained a lot of attention because their high security and easy transaction. Among the current cryptocurrencies, Bitcoin is the most well-known one. Application-specific ICs (ASICs) have been developed in order to deliver high throughput for Bitcoin mining. However, power dissipation is an important issue considering it causes increased mining cost and creates excessive heat. This paper presents three optimization techniques in the micro-architecture level for Bitcoin mining: deep pipelining, speculative computation, and approximate addition. The computations for Bitcoin milling are dominated by SHA-256, which can be realized by two-way 32-stage pipelines. Deep pipelining reduces the critical-path delay, resulting in less power due to architecture transformation and transistor sizing. The iterations of SHA-256 can be early terminated by leveraging speculative computation to prevent unnecessary switches. Approximate addition is adopted to reduce the critical-path delay of the compressor and expander at the cost of negligible precision loss. From the synthesis estimates at a 40-nm technology node, an overall 59.3% power reduction is achieved by applying these three techniques. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2019 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) | en_US |
dc.citation.spage | 0 | en_US |
dc.citation.epage | 0 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000480385400028 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |