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dc.contributor.authorChang, Tofar C. -Y.en_US
dc.contributor.authorWang, Pin-Hanen_US
dc.contributor.authorSu, Yu T.en_US
dc.date.accessioned2019-10-05T00:08:33Z-
dc.date.available2019-10-05T00:08:33Z-
dc.date.issued2019-09-01en_US
dc.identifier.issn1089-7798en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LCOMM.2019.2924210en_US
dc.identifier.urihttp://hdl.handle.net/11536/152768-
dc.description.abstractWe present two general multi-stage (MS) bit-flipping (BF) decoding algorithms for low-density parity-check (LDPC) codes. Both algorithms consist of soft-decision (SD) and hard-decision BF decoding parts. In comparison with known MS LDPC decoders, our approach is much simpler as all stages share the same BF structure. The only complexity increase is due to the use of an adaptive stage-switching (SS) mechanism which gives near-optimal SS timing. A new design issue we address is that the first-stage algorithm's parameter has to be re-tuned to achieve the optimal overall performance. The numerical results demonstrate that the proposed decoding methods can significantly improve the error-rate performance of the conventional SD BF decoders.en_US
dc.language.isoen_USen_US
dc.subjectLDPC codesen_US
dc.subjectbit-flipping decodingen_US
dc.subjectloop detectionen_US
dc.titleMulti-Stage Bit-Flipping Decoding Algorithms for LDPC Codesen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LCOMM.2019.2924210en_US
dc.identifier.journalIEEE COMMUNICATIONS LETTERSen_US
dc.citation.volume23en_US
dc.citation.issue9en_US
dc.citation.spage1524en_US
dc.citation.epage1528en_US
dc.contributor.department電機工程學系zh_TW
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000485733200017en_US
dc.citation.woscount0en_US
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