標題: HARDWARE-ORIENTED MEMORY-LIMITED ONLINE FASTICA ALGORITHM AND HARDWARE ARCHITECTURE FOR SIGNAL SEPARATION
作者: Van, Lan-Da
Lu, Tsung-Che
Jung, Tzyy-Ping
Wang, Jo-Fu
資訊工程學系
Department of Computer Science
關鍵字: Blind signal separation;EEG;component/channel switch;fast independent component analysis (FastICA);hardware implementation
公開日期: 1-Jan-2019
摘要: This paper presents a hardware-oriented memory-limited online FastICA algorithm and its hardware architecture and implementation for eight-channel electroencephalogram ( EEG) signal separation. The online algorithm integrates the data overlapping, garbage detection, channel permutation, and momentum-controlled weight update schemes to stabilize the order of the decomposed source signals across time. This study also realizes the algorithm into a hardware architecture and implementation with a core area of 1.469x1.469 mm(2) in a TSMC 90 nm process. The resulting power dissipation for eight-channel EEG signal separation is 65 mW@100 MHz at 1V.
URI: http://hdl.handle.net/11536/152924
ISBN: 978-1-4799-8131-1
ISSN: 1520-6149
期刊: 2019 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING (ICASSP)
起始頁: 1438
結束頁: 1442
Appears in Collections:Conferences Paper