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dc.contributor.authorTsai, Wei-Lunen_US
dc.contributor.authorChen, Sau-Geeen_US
dc.contributor.authorHuang, Shen-Juien_US
dc.date.accessioned2019-10-05T00:09:46Z-
dc.date.available2019-10-05T00:09:46Z-
dc.date.issued2019-01-01en_US
dc.identifier.isbn978-1-7281-0397-6en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/152956-
dc.description.abstractDue to the increasing demand for high-throughput and low-cost mobile devices, design of high-parallel reconfigurable FFT processors has become more and more important. However, FFT lengths varied, designing a multi-length FFT processor with the requirement meet has become unprecedentedly challenging, especially as the FFT lengths includes non-power-of-two. In this paper, reconfigurable mixed-radix 2(k)x3-point feedforward FFT architectures are proposed. It can be realized as any power-of-two parallelism to achieve the sweet spot, with performs high enough to meet the requirement and still promise a reasonable cost. A proposed feedforward radix-3 FFT is applied in the architecture, empowering the FFT processor to achieve high parallelisms. An 8-parallel 1282048/1536-point FFT processor for the 4G LTE system is implemented with TSMC 90nm technology. Compared to the existing designs, this work offers a high-throughput and high area-efficiency solution for mixed-radix FFT operation.en_US
dc.language.isoen_USen_US
dc.subjectFFTen_US
dc.subjectMDCen_US
dc.subjectmixed-radixen_US
dc.subjectnon-power-of-twoen_US
dc.titleReconfigurable Radix-2(k)x3 Feedforward FFT Architecturesen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)en_US
dc.citation.spage0en_US
dc.citation.epage0en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000483076401026en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper