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dc.contributor.authorYeh, Po-Chenen_US
dc.contributor.authorKuo, Chien-Nanen_US
dc.date.accessioned2019-10-05T00:09:47Z-
dc.date.available2019-10-05T00:09:47Z-
dc.date.issued2019-01-01en_US
dc.identifier.isbn978-1-7281-0397-6en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/152968-
dc.description.abstractA W-band low-noise amplifier consisting of seven common-source transistor stages is designed using noise measure as the figure of merit for circuit optimization. Fabricated in 90 nm CMOS technology, the die size is 0.38 mm(2), while the core active area only 0.1 mm(2). The circuit gives peak power gain of 21.5 dB at 90 GHz and noise figure of 8.3 dB, with dc power consumption of only 6.8 mW.en_US
dc.language.isoen_USen_US
dc.subjectCMOSen_US
dc.subjectLNAen_US
dc.subjectW-Banden_US
dc.subjectmillimeter-waveen_US
dc.subjectnoise measureen_US
dc.subjectlow-poweren_US
dc.titleA W-Band 6.8 mW Low-Noise Amplifier in 90 nm CMOS Technology Using Noise Measureen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)en_US
dc.citation.spage0en_US
dc.citation.epage0en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000483076403067en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper