Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yeh, Po-Chen | en_US |
dc.contributor.author | Kuo, Chien-Nan | en_US |
dc.date.accessioned | 2019-10-05T00:09:47Z | - |
dc.date.available | 2019-10-05T00:09:47Z | - |
dc.date.issued | 2019-01-01 | en_US |
dc.identifier.isbn | 978-1-7281-0397-6 | en_US |
dc.identifier.issn | 0271-4302 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/152968 | - |
dc.description.abstract | A W-band low-noise amplifier consisting of seven common-source transistor stages is designed using noise measure as the figure of merit for circuit optimization. Fabricated in 90 nm CMOS technology, the die size is 0.38 mm(2), while the core active area only 0.1 mm(2). The circuit gives peak power gain of 21.5 dB at 90 GHz and noise figure of 8.3 dB, with dc power consumption of only 6.8 mW. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | CMOS | en_US |
dc.subject | LNA | en_US |
dc.subject | W-Band | en_US |
dc.subject | millimeter-wave | en_US |
dc.subject | noise measure | en_US |
dc.subject | low-power | en_US |
dc.title | A W-Band 6.8 mW Low-Noise Amplifier in 90 nm CMOS Technology Using Noise Measure | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | en_US |
dc.citation.spage | 0 | en_US |
dc.citation.epage | 0 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000483076403067 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Conferences Paper |