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dc.contributor.authorSun, Wei-Cheen_US
dc.contributor.authorKuo, Chien-Nanen_US
dc.date.accessioned2019-12-13T01:12:53Z-
dc.date.available2019-12-13T01:12:53Z-
dc.date.issued2019-01-01en_US
dc.identifier.isbn978-1-7281-1309-8en_US
dc.identifier.issn0149-645Xen_US
dc.identifier.urihttp://hdl.handle.net/11536/153306-
dc.description.abstractA two-stage fully integrated 53-GHz stacked-FET power amplifier (PA) is implemented in 90-nm bulk CMOS. The output stage is optimized to achieve high output power while maintaining high power added efficiency (PAE). The complete PA achieves a measured saturated output power of 22.4 dBm and the 19.1% PAE at 2.4 V supply. It has -3 dB bandwidth of 8.8 GHz.en_US
dc.language.isoen_USen_US
dc.subjectamplifiersen_US
dc.subjectCMOSen_US
dc.subjectmillimeter waveen_US
dc.subjectpower amplifiersen_US
dc.subjectpower combineren_US
dc.subjecttransformersen_US
dc.subjectstacked transistorsen_US
dc.titleA 19.1% PAE, 22.4-dBm 53-GHz Parallel Power Combining Power Amplifier with Stacked-FET Techniques in 90-nm CMOSen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2019 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS)en_US
dc.citation.spage327en_US
dc.citation.epage330en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000494461700085en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper