A 19.1% PAE, 22.4-dBm 53-GHz Parallel Power Combining Power Amplifier with Stacked-FET Techniques in 90-nm CMOS

Full metadata record

DC Field	Value	Language
dc.contributor.author	Sun, Wei-Che	en_US
dc.contributor.author	Kuo, Chien-Nan	en_US
dc.date.accessioned	2019-12-13T01:12:53Z	-
dc.date.available	2019-12-13T01:12:53Z	-
dc.date.issued	2019-01-01	en_US
dc.identifier.isbn	978-1-7281-1309-8	en_US
dc.identifier.issn	0149-645X	en_US
dc.identifier.uri	http://hdl.handle.net/11536/153306	-
dc.description.abstract	A two-stage fully integrated 53-GHz stacked-FET power amplifier (PA) is implemented in 90-nm bulk CMOS. The output stage is optimized to achieve high output power while maintaining high power added efficiency (PAE). The complete PA achieves a measured saturated output power of 22.4 dBm and the 19.1% PAE at 2.4 V supply. It has -3 dB bandwidth of 8.8 GHz.	en_US
dc.language.iso	en_US	en_US
dc.subject	amplifiers	en_US
dc.subject	CMOS	en_US
dc.subject	millimeter wave	en_US
dc.subject	power amplifiers	en_US
dc.subject	power combiner	en_US
dc.subject	transformers	en_US
dc.subject	stacked transistors	en_US
dc.title	A 19.1% PAE, 22.4-dBm 53-GHz Parallel Power Combining Power Amplifier with Stacked-FET Techniques in 90-nm CMOS	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2019 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS)	en_US
dc.citation.spage	327	en_US
dc.citation.epage	330	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000494461700085	en_US
dc.citation.woscount	0	en_US
Appears in Collections:	Conferences Paper