The Impact of Layout Dependent Intrinsic Parasitic RLC on High Frequency Performance in 3T and 4T Multi-finger nMOSFETs

Abstract

A new observation of significant differences in the high frequency device parameters and performance like f(T) and f(MAX) is identified from the comparison of 3-terminal (3T) and 4-terminal (4T) multi-finger (MF) nMOSFETs. Through an extensive characterization on the intrinsic Z- and Y-parameters, it is found that the major impact comes from the particular increase of intrinsic parasitic resistances and inductances at the source terminal, namely R-s,R-int and L-s,L-int in the 4T MF MOSFETs. The proposed analytical models as a function of key device parameters incorporating the influence of the intrinsic parasitic RLC through high frequencies can accurately predict f(T) and f(MAX) degradation in 4T MF nMOSFETs as well as the complicated layout dependent effects. The experimental results and analytical models can be useful to facilitate MF devices layout optimization for high frequency design and performance improvement.