標題: The Understanding of Gate Capacitance Matching on Achieving a High Performance NC MOSFET with Sufficient Mobility
作者: Chiang, C. K.
Husan, P.
Lou, Y. C.
Li, F. L.
Hsieh, E. R.
Liu, C. H.
Chung, Steve S.
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-一月-2019
摘要: We develop experimental approaches to quantitatively extract the negative capacitance of MIM in a gate stacked NCFET. It was found that the NC effect is highly dependent on the grain and dipole behaviors with different annealing temperature. Also, to achieve a better design of high-performance NCFET, we explore not only the capacitance matching between ferroelectric HZO MIM and MOSFET but also how effective mobility is affected by HZO dipoles. For capacitance matching, we observe a 50x enhancement of overall gate capacitance triggered by NC effect, while, however, it adversely generated the degradation of the mobility. This mobility degradation is induced by the remote scattering from the ferroelectric HZO dipoles. Fortunately, if suitable polarization can be formed to align the HZO dipoles, the effects of remote scattering can be mitigated. From a trade-off between gate capacitance and the mobility, an NCFET with desirable performance can be achieved.
URI: http://hdl.handle.net/11536/153322
ISSN: 2161-4636
期刊: 2019 SILICON NANOELECTRONICS WORKSHOP (SNW)
起始頁: 103
結束頁: 104
顯示於類別:會議論文