Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Sung, P-J | en_US |
dc.contributor.author | Su, C-J | en_US |
dc.contributor.author | Lu, D. D. | en_US |
dc.contributor.author | Luo, S-X | en_US |
dc.contributor.author | Kao, K-H | en_US |
dc.contributor.author | Ciou, J-Y | en_US |
dc.contributor.author | Jao, C-Y | en_US |
dc.contributor.author | Hsu, H-S | en_US |
dc.contributor.author | Wang, C-J | en_US |
dc.contributor.author | Hong, T-C | en_US |
dc.contributor.author | Liao, T-H | en_US |
dc.contributor.author | Fang, C-C | en_US |
dc.contributor.author | Wang, Y-S | en_US |
dc.contributor.author | Huang, H-F | en_US |
dc.contributor.author | Li, J-H | en_US |
dc.contributor.author | Huang, Y-C | en_US |
dc.contributor.author | Hsueh, F-K | en_US |
dc.contributor.author | Wu, C-T | en_US |
dc.contributor.author | Ma, W. C-Y | en_US |
dc.contributor.author | Huang, K-P | en_US |
dc.contributor.author | Lee, Y-J | en_US |
dc.contributor.author | Chao, T-S | en_US |
dc.contributor.author | Li, J-Y | en_US |
dc.contributor.author | Wu, W-F | en_US |
dc.contributor.author | Yeh, W-K | en_US |
dc.contributor.author | Wang, Y-H | en_US |
dc.date.accessioned | 2020-02-02T23:55:33Z | - |
dc.date.available | 2020-02-02T23:55:33Z | - |
dc.date.issued | 2019-01-01 | en_US |
dc.identifier.isbn | 978-1-7281-0942-8 | en_US |
dc.identifier.issn | 1930-8868 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/153667 | - |
dc.description.abstract | Omega-gated negative capacitance (NC) FinFETs, CMOS inverters and SRAM are fabricated and analyzed. Forming gas annealing (FGA) is performed and found to not only enhance ferroelectricity (FE) but also the NCFET electrostatics, in terms of higher I-ON, smaller hysteresis and subthreshold slop (SS). The SS is less than 60 mV/dec for both N-FinFET and P-FinFET in this work. Moreover, the CMOS inverter shows more symmetric and larger voltage gain after FGA. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Fabrication of Omega-gated Negative Capacitance FinFETs and SRAM | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2019 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA) | en_US |
dc.citation.spage | 0 | en_US |
dc.citation.epage | 0 | en_US |
dc.contributor.department | 電子物理學系 | zh_TW |
dc.contributor.department | Department of Electrophysics | en_US |
dc.identifier.wosnumber | WOS:000503374900020 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Conferences Paper |