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dc.contributor.authorTseng, Kuei-Yangen_US
dc.contributor.authorYou, Wei-Xiangen_US
dc.contributor.authorSu, Pinen_US
dc.date.accessioned2020-02-02T23:55:33Z-
dc.date.available2020-02-02T23:55:33Z-
dc.date.issued2019-01-01en_US
dc.identifier.isbn978-1-7281-0942-8en_US
dc.identifier.issn1930-8868en_US
dc.identifier.urihttp://hdl.handle.net/11536/153669-
dc.description.abstractIn this work, we comprehensively evaluate and analyze the stability and performance of 6T SRAM cells using 2D MFIS-type negative capacitance FETs (2D-NCFETs) based on the IRDS 2030 node with 10-nm gate length. Our results indicate that 2D-NCFETs possess better RSNM than the 2D-FET counterpart under low supply voltages. Our study also shows that 2D-NCFETs have better WSNM except for V-DD = 0.2V due to the existence of hysteresis loop in write curve during write operation. By using write-assist circuits or back-gating techniques, we demonstrate that the WSNM of 2D-NCFETs can be significantly improved. We further analyze the performance of read and write operations, and 2D-NCFETs have been found to possess better performance than 2D-FETs.en_US
dc.language.isoen_USen_US
dc.titleEvaluation of 2D Negative-Capacitance FETs for Low-Voltage SRAM Applicationsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2019 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA)en_US
dc.citation.spage0en_US
dc.citation.epage0en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000503374900047en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper