完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Tseng, Kuei-Yang | en_US |
dc.contributor.author | You, Wei-Xiang | en_US |
dc.contributor.author | Su, Pin | en_US |
dc.date.accessioned | 2020-02-02T23:55:33Z | - |
dc.date.available | 2020-02-02T23:55:33Z | - |
dc.date.issued | 2019-01-01 | en_US |
dc.identifier.isbn | 978-1-7281-0942-8 | en_US |
dc.identifier.issn | 1930-8868 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/153669 | - |
dc.description.abstract | In this work, we comprehensively evaluate and analyze the stability and performance of 6T SRAM cells using 2D MFIS-type negative capacitance FETs (2D-NCFETs) based on the IRDS 2030 node with 10-nm gate length. Our results indicate that 2D-NCFETs possess better RSNM than the 2D-FET counterpart under low supply voltages. Our study also shows that 2D-NCFETs have better WSNM except for V-DD = 0.2V due to the existence of hysteresis loop in write curve during write operation. By using write-assist circuits or back-gating techniques, we demonstrate that the WSNM of 2D-NCFETs can be significantly improved. We further analyze the performance of read and write operations, and 2D-NCFETs have been found to possess better performance than 2D-FETs. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Evaluation of 2D Negative-Capacitance FETs for Low-Voltage SRAM Applications | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2019 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA) | en_US |
dc.citation.spage | 0 | en_US |
dc.citation.epage | 0 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000503374900047 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |