Device Structural Effects, SPICE Modeling and Circuit Evaluation for Negative-Capacitance FETs

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Su, Pin	en_US
dc.contributor.author	You, Wei-Xiang	en_US
dc.date.accessioned	2020-02-02T23:55:33Z	-
dc.date.available	2020-02-02T23:55:33Z	-
dc.date.issued	2019-01-01	en_US
dc.identifier.isbn	978-1-7281-0942-8	en_US
dc.identifier.issn	1930-8868	en_US
dc.identifier.uri	http://hdl.handle.net/11536/153670	-
dc.language.iso	en_US	en_US
dc.title	Device Structural Effects, SPICE Modeling and Circuit Evaluation for Negative-Capacitance FETs	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2019 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA)	en_US
dc.citation.spage	0	en_US
dc.citation.epage	0	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000503374900050	en_US
dc.citation.woscount	0	en_US
顯示於類別：	會議論文

APA	Su, P., & You, W. (2019). Device Structural Effects, SPICE Modeling and Circuit Evaluation for Negative-Capacitance FETs. WOS:000503374900050.
Bibtex	@article{Su2019Device, title={Device Structural Effects, SPICE Modeling and Circuit Evaluation for Negative-Capacitance FETs}, author={Su, Pin and You, Wei-Xiang}, journal={WOS:000503374900050}, year={2019}, url={https://ir.lib.nycu.edu.tw/handle/11536/153670?mode=full}, }