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dc.contributor.authorChang, You-Taien_US
dc.contributor.authorTsai, Yueh-Linen_US
dc.contributor.authorPeng, Kang-Pingen_US
dc.contributor.authorSu, Chun-Jungen_US
dc.contributor.authorLi, Pei-Wenen_US
dc.contributor.authorLin, Horng-Chihen_US
dc.date.accessioned2020-05-05T00:02:22Z-
dc.date.available2020-05-05T00:02:22Z-
dc.date.issued2020-04-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.7567/1347-4065/ab5b67en_US
dc.identifier.urihttp://hdl.handle.net/11536/154174-
dc.description.abstractIn this Paper, we investigated random telegraph noise (RTN) characteristics of gate-all-around poly-Si nanowire (NW) transistors with high-kappa oxide/metal-gate (HK/MG) stack. Distinct two-level RTN signals were measured on NW transistors with effective channel length of 150 nm and channel width of 30 nm. Values of time constants for charge emission from and capture by traps were extracted from measured RTN signals We proposed a new theoretical scheme to evaluate the location and energy level of the corresponding trap. The trap was assessed to be present within the interfacial layer (IL) at a spatial location approximate 1 nm away from the IL/channel interface and 68 nm in proximity to the source side. (C) 2020 The Japan Society of Applied Physicsen_US
dc.language.isoen_USen_US
dc.titleStudy on random telegraph noise of high-idmetal-gate gate-all-around poly-Si nanowire transistorsen_US
dc.typeArticleen_US
dc.identifier.doi10.7567/1347-4065/ab5b67en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICSen_US
dc.citation.volume59en_US
dc.citation.spage0en_US
dc.citation.epage0en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000519630000009en_US
dc.citation.woscount0en_US
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