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dc.contributor.authorLiu, You-Shengen_US
dc.contributor.authorSu, Pinen_US
dc.date.accessioned2020-05-05T00:02:23Z-
dc.date.available2020-05-05T00:02:23Z-
dc.date.issued2020-03-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2020.2967423en_US
dc.identifier.urihttp://hdl.handle.net/11536/154183-
dc.description.abstractThis paper investigates the impact of the random ferroelectric-dielectric (FE-DE) phase distribution on the memory window (MW) of the ferroelectric field-effect transistor (FeFET) nonvolatile memory (NVM) with the aid of TCAD atomistic simulations. Our study indicates that the DE path from source to drain is detrimental to the MW, and down-scaling the gate length substantially increases the probability of forming DE path and the variability in the MW. In addition, the MW variability for scaled FeFET devices can be mitigated by reducing the grain size, even under the same grain-to-channel area ratio. Besides, when down-scaling the insulator thickness to increase the MW, the increased MW variability due to the random FE-DE grains needs to be considered. Our study may provide insights for future scaling of FeFET NVMs.en_US
dc.language.isoen_USen_US
dc.subjectFerroelectric field-effect transistor (FeFET)en_US
dc.subjectmemory window (MW)en_US
dc.subjectrandom variationen_US
dc.subjectnonvolatile memory (NVM)en_US
dc.titleVariability Analysis for Ferroelectric FET Nonvolatile Memories Considering Random Ferroelectric-Dielectric Phase Distributionen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2020.2967423en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume41en_US
dc.citation.issue3en_US
dc.citation.spage369en_US
dc.citation.epage372en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000519704300015en_US
dc.citation.woscount0en_US
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