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dc.contributor.authorLopez, Henryen_US
dc.contributor.authorChan, Hsun-Weien_US
dc.contributor.authorChiu, Kang-Lunen_US
dc.contributor.authorTsai, Pei-Yunen_US
dc.contributor.authorJou, Shyh-Jye Jerryen_US
dc.date.accessioned2020-05-05T00:02:26Z-
dc.date.available2020-05-05T00:02:26Z-
dc.date.issued2020-04-01en_US
dc.identifier.issn1063-8210en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TVLSI.2019.2955925en_US
dc.identifier.urihttp://hdl.handle.net/11536/154242-
dc.description.abstractThis article presents a high-throughput and low-routing complexity low-density parity check (LDPC) decoder design based on a novel second minimum approximation min-sum (SAMS) algorithm. The routing congestion is mitigated by reducing the required interconnections in the critical path of the routing network. The implementation and postlayout results with 28-nm 1P9M CMOS process show that the proposed design can achieve a throughput of 10.5 Gb/s for a millimeter-wave 60-GHz baseband system while satisfying the low bit error rate (BER) requirements (10(-7)). The proposed design reduces the wiring in the routing network by 21% and improves the area by 12% compared to the conventional min-sum (MS) and normalized MS (NMS) algorithm. Additional hardware optimizations are obtained by considering the internal message passing resolution based on the BER and signal-to-noise ratio (SNR) requirements for a practical baseband system. The power consumption is efficiently reduced by the employment of a shared address generator that exploits the degree of parallelism to reduce the switching activity on a group of memory elements. The LDPC decoder is implemented with a core area of 0.14 mm(2), power consumption of 81 mW at 312.5 MHz, and the area and power efficiency of 75 Gb/s/mm(2) and 10.2 pJ/bit, respectively.en_US
dc.language.isoen_USen_US
dc.subjectLow-density parity check (LDPC) decoderen_US
dc.subjectmin-sum (MS) algorithmen_US
dc.subjectnormalized MS (NMS)en_US
dc.subjectoffset MS (OMS)en_US
dc.titleA 75-Gb/s/mm(2) and Energy-Efficient LDPC Decoder Based on a Reduced Complexity Second Minimum Approximation Min-Sum Algorithmen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TVLSI.2019.2955925en_US
dc.identifier.journalIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMSen_US
dc.citation.volume28en_US
dc.citation.issue4en_US
dc.citation.spage926en_US
dc.citation.epage939en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000522421700007en_US
dc.citation.woscount0en_US
Appears in Collections:Articles