Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lin, Dave Y. -W. | en_US |
dc.contributor.author | Wen, Charles H. -P. | en_US |
dc.date.accessioned | 2020-05-05T00:02:26Z | - |
dc.date.available | 2020-05-05T00:02:26Z | - |
dc.date.issued | 2020-04-01 | en_US |
dc.identifier.issn | 1063-8210 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TVLSI.2019.2962080 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/154243 | - |
dc.description.abstract | For the safety-critical applications such as biomedical and automobile electronics, the system failure induced by soft errors becomes a major issue of reliability. However, most of the commercial cell libraries do not include radiation-hardened components to build a safety-critical design. Therefore, a delay-adjustable D-flip-flop (DAD-FF) is proposed together with a design flow to construct a radiation-hardened system by automation. To enable such radiation-hardened design into the current design flow, DAD-FF is characterized as a general cell and compiled as a patch in the NanGate FreePDK45 bulk 45-nm open cell library, as an example. The experimental results show that DAD-FF is capable of reducing $1.3\times 10<^>{10}\text{X}$ soft errors with respect to the standard flip-flop (STD-FF) and resisting over 99.999997% strikes of heavy ions. Meanwhile, four radiation-hardened benchmark circuits are synthesized with DAD-FF cell, and further used to prove the effectiveness against soft errors compared to a prior work, built-in soft-error resilience (BISER), with 18% area and 40% timing improvement. To sum up, DAD-FF is elaborated from the modeling at the device-level to the validation at the system-level and exhibits its strong robustness to soft errors. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Characterization | en_US |
dc.subject | design flow | en_US |
dc.subject | flip-flops | en_US |
dc.subject | heavy ion | en_US |
dc.subject | radiation hardening | en_US |
dc.subject | semiconductor device modeling | en_US |
dc.subject | singleevent transient (SET) | en_US |
dc.subject | soft error | en_US |
dc.subject | technology computer-aided design (TCAD) simulation | en_US |
dc.title | DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reduction | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TVLSI.2019.2962080 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | en_US |
dc.citation.volume | 28 | en_US |
dc.citation.issue | 4 | en_US |
dc.citation.spage | 1030 | en_US |
dc.citation.epage | 1042 | en_US |
dc.contributor.department | 電機工程學系 | zh_TW |
dc.contributor.department | Department of Electrical and Computer Engineering | en_US |
dc.identifier.wosnumber | WOS:000522421700015 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Articles |