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dc.contributor.authorLin, Dave Y. -W.en_US
dc.contributor.authorWen, Charles H. -P.en_US
dc.date.accessioned2020-05-05T00:02:26Z-
dc.date.available2020-05-05T00:02:26Z-
dc.date.issued2020-04-01en_US
dc.identifier.issn1063-8210en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TVLSI.2019.2962080en_US
dc.identifier.urihttp://hdl.handle.net/11536/154243-
dc.description.abstractFor the safety-critical applications such as biomedical and automobile electronics, the system failure induced by soft errors becomes a major issue of reliability. However, most of the commercial cell libraries do not include radiation-hardened components to build a safety-critical design. Therefore, a delay-adjustable D-flip-flop (DAD-FF) is proposed together with a design flow to construct a radiation-hardened system by automation. To enable such radiation-hardened design into the current design flow, DAD-FF is characterized as a general cell and compiled as a patch in the NanGate FreePDK45 bulk 45-nm open cell library, as an example. The experimental results show that DAD-FF is capable of reducing $1.3\times 10<^>{10}\text{X}$ soft errors with respect to the standard flip-flop (STD-FF) and resisting over 99.999997% strikes of heavy ions. Meanwhile, four radiation-hardened benchmark circuits are synthesized with DAD-FF cell, and further used to prove the effectiveness against soft errors compared to a prior work, built-in soft-error resilience (BISER), with 18% area and 40% timing improvement. To sum up, DAD-FF is elaborated from the modeling at the device-level to the validation at the system-level and exhibits its strong robustness to soft errors.en_US
dc.language.isoen_USen_US
dc.subjectCharacterizationen_US
dc.subjectdesign flowen_US
dc.subjectflip-flopsen_US
dc.subjectheavy ionen_US
dc.subjectradiation hardeningen_US
dc.subjectsemiconductor device modelingen_US
dc.subjectsingleevent transient (SET)en_US
dc.subjectsoft erroren_US
dc.subjecttechnology computer-aided design (TCAD) simulationen_US
dc.titleDAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reductionen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TVLSI.2019.2962080en_US
dc.identifier.journalIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMSen_US
dc.citation.volume28en_US
dc.citation.issue4en_US
dc.citation.spage1030en_US
dc.citation.epage1042en_US
dc.contributor.department電機工程學系zh_TW
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000522421700015en_US
dc.citation.woscount0en_US
Appears in Collections:Articles