標題: | DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reduction |
作者: | Lin, Dave Y. -W. Wen, Charles H. -P. 電機工程學系 Department of Electrical and Computer Engineering |
關鍵字: | Characterization;design flow;flip-flops;heavy ion;radiation hardening;semiconductor device modeling;singleevent transient (SET);soft error;technology computer-aided design (TCAD) simulation |
公開日期: | 1-四月-2020 |
摘要: | For the safety-critical applications such as biomedical and automobile electronics, the system failure induced by soft errors becomes a major issue of reliability. However, most of the commercial cell libraries do not include radiation-hardened components to build a safety-critical design. Therefore, a delay-adjustable D-flip-flop (DAD-FF) is proposed together with a design flow to construct a radiation-hardened system by automation. To enable such radiation-hardened design into the current design flow, DAD-FF is characterized as a general cell and compiled as a patch in the NanGate FreePDK45 bulk 45-nm open cell library, as an example. The experimental results show that DAD-FF is capable of reducing $1.3\times 10<^>{10}\text{X}$ soft errors with respect to the standard flip-flop (STD-FF) and resisting over 99.999997% strikes of heavy ions. Meanwhile, four radiation-hardened benchmark circuits are synthesized with DAD-FF cell, and further used to prove the effectiveness against soft errors compared to a prior work, built-in soft-error resilience (BISER), with 18% area and 40% timing improvement. To sum up, DAD-FF is elaborated from the modeling at the device-level to the validation at the system-level and exhibits its strong robustness to soft errors. |
URI: | http://dx.doi.org/10.1109/TVLSI.2019.2962080 http://hdl.handle.net/11536/154243 |
ISSN: | 1063-8210 |
DOI: | 10.1109/TVLSI.2019.2962080 |
期刊: | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS |
Volume: | 28 |
Issue: | 4 |
起始頁: | 1030 |
結束頁: | 1042 |
顯示於類別: | 期刊論文 |