完整後設資料紀錄
DC 欄位語言
dc.contributor.authorLee, Chia-Hsinen_US
dc.contributor.authorSu, Jayen_US
dc.contributor.authorLiu, Xiaoen_US
dc.contributor.authorWu, Qien_US
dc.contributor.authorLin, Jim-Weinen_US
dc.contributor.authorLin, Puruen_US
dc.contributor.authorKo, Cheng-Taen_US
dc.contributor.authorChen, Yu-Huaen_US
dc.contributor.authorShen, Wen-Weien_US
dc.contributor.authorKou, Tzu-Yingen_US
dc.contributor.authorHuang, Shin-Yien_US
dc.contributor.authorLin, Ang-Yingen_US
dc.contributor.authorLin, Yu-Minen_US
dc.contributor.authorChen, Kuan-Nengen_US
dc.date.accessioned2020-07-01T05:21:48Z-
dc.date.available2020-07-01T05:21:48Z-
dc.date.issued2018-01-01en_US
dc.identifier.isbn978-1-5386-4998-5en_US
dc.identifier.issn0569-5503en_US
dc.identifier.urihttp://dx.doi.org/10.1109/ECTC.2018.00273en_US
dc.identifier.urihttp://hdl.handle.net/11536/154484-
dc.description.abstractFan-out wafer-level-packaging (FOWLP) technology has been developed with various advantages, such as smaller form factor, lower cost, and simplified supply chain for heterogeneous integration. There have been several process schemes like chip-first or chip-last FOWLP integration discussed widely in conferences in recent years. One process in all of these process schemes has in common is the use of a temporary carrier for subsequent redistribution layer (RDL) formation, chip stacking and molding processes. Although the separation of a temporary carrier from the reconstituted wafer could be achieved without significant hurdles, there were few studies addressing optimization of carrier separation for throughput enhancement. Thus, this paper is designed to address the needs in optimizing carrier separation process based upon laser ablation technology. Two phases of experiments were designed to select the appropriate laser release layer and define optimal laser settings. The first experiment was used to evaluate correlation of the laser absorption, laser energy, and spot pitch versus completeness of laser ablation. The second experiment included RDL-first FOWLP integration. At first, 300-mm glass carriers (1000 mu m thick) with coefficient of thermal expansion of 8 ppm/degrees C were treated by selected laser release layers. After deposition of 0.05-mu m Ti/0.15 mu m Cu on the glass carrier, passivation of around 8 mu m was coated and patterned by lithography for electroplating Cu interconnections with a density of approximately 10% of the surface area. Subsequently, die bonding, build-up layers, or molding compound were applied on top to form a 200-mu m reconstituted wafer. The reconstituted wafer was then separated from the glass carrier through a laser ablation process using a 355-nm laser to determine optimal throughput. Experiments to study correlation of laser release layer with laser settings along with a demonstration of full RDL-first FOWLP integration are discussed thoroughly to address the need of throughput enhancement, which could serve as cornerstone for realizing cost-effective RDL-first FOWLP.en_US
dc.language.isoen_USen_US
dc.subjectFan-out wafer level packagingen_US
dc.subjectFOWLPen_US
dc.subjectRDL-firsten_US
dc.subjectlaser releaseen_US
dc.titleOptimization of laser release process for throughput enhancement of fan-out wafer-level packagingen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/ECTC.2018.00273en_US
dc.identifier.journal2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018)en_US
dc.citation.spage1824en_US
dc.citation.epage1829en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000514675100266en_US
dc.citation.woscount1en_US
顯示於類別:會議論文