完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.author | Elangovan, Surya | en_US |
dc.contributor.author | Cheng, Stone | en_US |
dc.contributor.author | Chang, Edward Yi | en_US |
dc.date.accessioned | 2020-07-01T05:22:07Z | - |
dc.date.available | 2020-07-01T05:22:07Z | - |
dc.date.issued | 2020-05-01 | en_US |
dc.identifier.uri | http://dx.doi.org/10.3390/en13102628 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/154525 | - |
dc.description.abstract | We present a detailed study of dynamic switching instability and static reliability of a Gallium Nitride (GaN) Metal-Insulator-Semiconductor High-Electron-Mobility-Transistor (MIS-HEMT) based cascode switch under off-state (negative bias) Gate bias stress (V-GS,V- OFF). We have investigated drain channel current (I-DS,I- Max) collapse/degradation and turn-on and rise-time (t(R)) delay, on-state resistance (RDS-ON) and maximum transconductance (G(m, max)) degradation and threshold voltage (V-TH) shift for pulsed and prolonged off-state gate bias stress V-GS,V- OFF. We have found that as stress voltage magnitude and stress duration increases, similarly I-DS,I- Max and RDS-ON degradation, V-TH shift and turn-on/rise time (t(R)) delay, and G(m, max) degradation increases. In a pulsed off-state V-GS,V- OFF stress experiment, the device instabilities and degradation with electron trapping effects are studied through two regimes of stress voltages. Under low stress, V-TH shift, I-DS collapse, RDS-ON degradation has very minimal changes, which is a result of a recoverable surface state trapping effect. For high-stress voltages, there is an increased and permanent V-TH shift and high I-DS,I- Max and RDS-ON degradation in pulsed V-GS,V- Stress and increased rise-time and turn-on delay. In addition to this, a positive V-TH shift and G(m, max) degradation were observed in prolonged stress experiments for selected high-stress voltages, which is consistent with interface state generation. These findings provide a path to understand the failure mechanisms under room temperature and also to accelerate the developments of emerging GaN cascode technologies. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | gallium nitride HEMT | en_US |
dc.subject | cascode configuration | en_US |
dc.subject | off-state gate bias stress | en_US |
dc.subject | device degradation | en_US |
dc.subject | failure mechanisms | en_US |
dc.subject | electronic trapping effects | en_US |
dc.title | Reliability Characterization of Gallium Nitride MIS-HEMT Based Cascode Devices for Power Electronic Applications | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.3390/en13102628 | en_US |
dc.identifier.journal | ENERGIES | en_US |
dc.citation.volume | 13 | en_US |
dc.citation.issue | 10 | en_US |
dc.citation.spage | 0 | en_US |
dc.citation.epage | 0 | en_US |
dc.contributor.department | 機械工程學系 | zh_TW |
dc.contributor.department | 材料科學與工程學系 | zh_TW |
dc.contributor.department | Department of Mechanical Engineering | en_US |
dc.contributor.department | Department of Materials Science and Engineering | en_US |
dc.identifier.wosnumber | WOS:000539257300220 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |