完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Huang, Juinn-Dar | en_US |
dc.contributor.author | Chen, Yi-Hang | en_US |
dc.contributor.author | Lin, Wan-Hsien | en_US |
dc.date.accessioned | 2014-12-08T15:21:45Z | - |
dc.date.available | 2014-12-08T15:21:45Z | - |
dc.date.issued | 2011 | en_US |
dc.identifier.isbn | 978-1-4244-8499-7 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/15483 | - |
dc.description.abstract | Since utilizing compound functional units (e. g., multiplier-accumulate) designed with shorter delay and/or smaller area than cascaded basic functional units is a well-known technique in system design, this paper presents an ILP-based approach for performance-driven behavioral synthesis with compound functional units. The algorithm maximizes the performance of a design under resource constraints by deriving all possible degenerative forms of compound functional units and by maximizing the utilization of resources. The proposed method exploits patterns acquired from available resource types to cover the target design optimally, and then guarantees that the synthesis result is with minimal latency. Experimental results show that our approach achieves significant performance improvement as compared with the prior art. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Performance-Optimal Behavioral Synthesis with Degenerable Compound Functional Units | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2011 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) | en_US |
dc.citation.spage | 337 | en_US |
dc.citation.epage | 340 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000300488600074 | - |
顯示於類別: | 會議論文 |