標題: -65dB HD3 CMOS TUNABLE OTA WITH MOBILITY REDUCTION COMPENSATION
作者: Cheng, Shih-Tung
Chang, Wei-Hsiu
Hung, Chung-Chih
電機工程學系
Department of Electrical and Computer Engineering
公開日期: 2011
摘要: This paper presents a high linearity operational transconductance amplifier (OTA) base on the technique of mobility reduction compensation, which achieves great linearity improvement and has wide input range at low power consumption. The third-order harmonic distortion (HD3) of the OTA is about -65dB at 1MHz for a 1.2-V-pp differential input. The OTA was designed by the TSMC 0.18-mu m CMOS process technology. For 1.8-V supply voltage, the static power consumption is only 0.427mW.
URI: http://hdl.handle.net/11536/15484
ISBN: 978-1-4244-8499-7
期刊: 2011 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)
起始頁: 358
結束頁: 361
顯示於類別:會議論文