完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Tu, Hong-Yi | en_US |
dc.contributor.author | Chang, Ting-Chang | en_US |
dc.contributor.author | Tsao, Yu-Ching | en_US |
dc.contributor.author | Tai, Mao-Chou | en_US |
dc.contributor.author | Tsai, Yu-Lin | en_US |
dc.contributor.author | Huang, Shin-Ping | en_US |
dc.contributor.author | Zheng, Yu-Zhe | en_US |
dc.contributor.author | Wang, Yu-Xuan | en_US |
dc.contributor.author | Lin, Chih-Chih | en_US |
dc.contributor.author | Kuo, Chuan-Wei | en_US |
dc.contributor.author | Tsai, Tsung-Ming | en_US |
dc.contributor.author | Wu, Chia-Chuan | en_US |
dc.contributor.author | Chien, Ya-Ting | en_US |
dc.contributor.author | Huang, Hui-Chun | en_US |
dc.date.accessioned | 2020-10-05T02:01:10Z | - |
dc.date.available | 2020-10-05T02:01:10Z | - |
dc.date.issued | 2020-09-30 | en_US |
dc.identifier.issn | 0022-3727 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1088/1361-6463/ab9918 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/155202 | - |
dc.description.abstract | Degradation in low-temperature polycrystalline-silicon thin-film transistors after electrical stress was thoroughly investigated in this work. Main channel degradation, abnormal hump generation and hysteresis appearing in the hump region can be observed after positive bias stress. Furthermore, the difference in subthreshold swing (SS) values between forward/reverse sweep is observed. The electron trapping into the gate insulator (GI) dominates the main degradation and the hump generation. Additionally, the difference in SS values which appears in the hump region is attributed to the interface traps and the hysteresis is caused by electron trapping/detrapping into GI. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | low-temperature polycrystalline-silicon thin-film transistor | en_US |
dc.subject | dual sweep operation | en_US |
dc.subject | abnormal hump | en_US |
dc.subject | hysteresis | en_US |
dc.title | Abnormal hysteresis formation in hump region after positive gate bias stress in low-temperature poly-silicon thin film transistors | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1088/1361-6463/ab9918 | en_US |
dc.identifier.journal | JOURNAL OF PHYSICS D-APPLIED PHYSICS | en_US |
dc.citation.volume | 53 | en_US |
dc.citation.issue | 40 | en_US |
dc.citation.spage | 0 | en_US |
dc.citation.epage | 0 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000553715200001 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |