標題: | Translating AArch64 Floating-Point Instruction Set to the x86-64 Platform |
作者: | You, Yi-Ping Lin, Tsung-Chun Yang, Wuu 資訊工程學系 Department of Computer Science |
關鍵字: | AArch64;ARM v8;x86-64;binary translation;LLVM;mc2llvm |
公開日期: | 1-一月-2019 |
摘要: | Binary translation translates binary programs from one instruction set to another. It is widely used in virtual machines and emulators. We extend mc2llvm, which is an LLVM-based retargetable 32-bit binary translator developed in our lab in the past several years, to support 64-bit ARM instruction set. In this paper, we report the translation of AArch64 floating-point instructions in our mc2llvm. For floating-point instructions, due to the lack of floating-point support in LLVM [13, 14], we add support for the flush-to-zero mode, not-a-number processing, floating-point exceptions, and various rounding modes. On average, mc2llvm-translated binary can achieve 47% and 24.5% of the performance of natively compiled x86-64 binary on statically translated EEMBC benchmark and dynamically translated SPEC CINT2006 benchmarks, respectively. Compared to QEMU-translated binary, mc2llvm-translated binary runs 2.92x, 1.21x and 1.41x faster on statically translated EEMBC benchmark, dynamically translated SPEC CINT2006, and CFP2006 benchmarks, respectively. (Note that the benchmarks contain both floating-point instructions and other instructions, such as load and store instructions.) |
URI: | http://dx.doi.org/10.1145/3339186.3339192 http://hdl.handle.net/11536/155292 |
ISBN: | 978-1-4503-7196-4 |
DOI: | 10.1145/3339186.3339192 |
期刊: | PROCEEDINGS OF THE 48TH INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING WORKSHOPS (ICPP 2019) |
起始頁: | 0 |
結束頁: | 0 |
顯示於類別: | 會議論文 |