A 188-size 2.1mm(2) Reconfigurable Turbo Decoder Chip with Parallel Architecture for 3GPP LTE System

Full metadata record

DC Field	Value	Language
dc.contributor.author	Wong, Cheng-Chi	en_US
dc.contributor.author	Lee, Yung-Yu	en_US
dc.contributor.author	Chang, Hsie-Chia	en_US
dc.date.accessioned	2014-12-08T15:21:54Z	-
dc.date.available	2014-12-08T15:21:54Z	-
dc.date.issued	2009	en_US
dc.identifier.isbn	978-4-86348-010-0	en_US
dc.identifier.uri	http://hdl.handle.net/11536/15598	-
dc.description.abstract	This paper presents a turbo decoder chip supporting all 188 block sizes in 3GPP LTE standard. The design allows 1, 2, 4, or 8 SISO decoders to concurrently process each block size, and the number of iteration can be adjusted. Moreover, a three-stage network is utilized to connect multiple memory modules and multiple SISO decoders. After fabricated in 90nm process, the 2.1mm(2) chip can achieve 129Mb/s with 219mW for the 6144-bit block after 8 iterations.	en_US
dc.language.iso	en_US	en_US
dc.subject	3GPP LTE	en_US
dc.subject	turbo decoder	en_US
dc.subject	QPP interleaver	en_US
dc.title	A 188-size 2.1mm(2) Reconfigurable Turbo Decoder Chip with Parallel Architecture for 3GPP LTE System	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS	en_US
dc.citation.spage	288	en_US
dc.citation.epage	289	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000274325200112	-
Appears in Collections:	Conferences Paper