Design of High-Performance and Highly Reliable nMOSFETs with Embedded Si:C S/D Extension Stressor(Si:C S/D-E)

標題:	Design of High-Performance and Highly Reliable nMOSFETs with Embedded Si:C S/D Extension Stressor(Si:C S/D-E)
作者:	Chung, Steve S. Hsieh, E. R. Liu, P. W. Chiang, W. T. Tsai, S. H. Tsai, T. L. Huang, R. M. Tsai, C. H. Teng, W. Y. Li, C. I. Kuo, T. F. Wang, Y. R. Yang, C. L. Tsai, C. T. Ma, G. H. Chien, S. C. Sun, S. W. 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
關鍵字:	embedded SiC;strained technology;CMOS;Positive Temperature Bias Instability
公開日期:	2009
摘要:	A Novel strained nMOSFET with embedded Si:C in S/D extension stressor (Si:C S/D-E) was presented. Comparing to the bulk device, it revealed good drive current ION (+27%), high I(D.sat) current (+67%), enhanced channel mobility (+105%), at a lower effective substitutional carbon concentration (C%-1.1%), using the poly-gate 40nm-node Si:C/eSiGe S/D CMOS technology. Moreover. PBTI effect was first observed in this device as a result of Carbn impurity out-diffusion, which is of critically important for the design trade-off between performance and reliability.
URI:	http://hdl.handle.net/11536/15620
ISBN:	978-4-86348-009-4
期刊:	2009 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS
起始頁:	158
結束頁:	159
顯示於類別：	會議論文