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dc.contributor.authorLin, Shun-Huaen_US
dc.contributor.authorYan, Jin-Taien_US
dc.contributor.authorChiueh, Hermingen_US
dc.date.accessioned2014-12-08T15:02:59Z-
dc.date.available2014-12-08T15:02:59Z-
dc.date.issued2008en_US
dc.identifier.isbn978-1-4244-3365-0en_US
dc.identifier.urihttp://hdl.handle.net/11536/1575-
dc.description.abstractThermal issues have become a determinant factor to result in very large scale integrated (VGSI) circuits work or malfunction. For this reason, the paper proposed an efficient block-level thermal model for temperature calculation in the floorplan stage among the integrated circuit (IC) design flow. Furthermore, the model accurately profiles the temperature difference between all thermal blocks and overcomes the very long computational time issue existing in traditional tile-based thermal model. We not only prove the timing complexity by theory but also use five floorplan benchmarks to test our model. Observing the experimental results, the temperature calculation times for all benchmarks are really direct ratio of total amount of blocks. Hence our block-level thermal model really can reduce the temperature calculating time and provide useful temperature differences for rearranging the floorplan.en_US
dc.language.isoen_USen_US
dc.titleBlock-Level Thermal Model for Floorplan Stage in VLSI Design Flowen_US
dc.typeProceedings Paperen_US
dc.identifier.journal14TH INTERNATIONAL WORKSHOP ON THERMAL INVESTIGATION OF ICS AND SYSTEMSen_US
dc.citation.spage58en_US
dc.citation.epage63en_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000265212200011-
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