完整後設資料紀錄
DC 欄位語言
dc.contributor.authorChou, Hsiu-Yuen_US
dc.contributor.authorLee, En-Koen_US
dc.contributor.authorLin, Meng-Hanen_US
dc.contributor.authorTseng, Tseung-Yuenen_US
dc.date.accessioned2014-12-08T15:22:32Z-
dc.date.available2014-12-08T15:22:32Z-
dc.date.issued2009-01-01en_US
dc.identifier.issn0015-0193en_US
dc.identifier.urihttp://dx.doi.org/10.1080/00150190902869913en_US
dc.identifier.urihttp://hdl.handle.net/11536/15928-
dc.description.abstractLow temperature processing of SBT thin films with SrTiO(3) (STO) seeded layer deposited onto Ir/SiO(2)/Si (MIM structure) and CeO(2)/Si (MFIS structure) substrate using MOD method was investigated. The Sr(0.8)Bi(2.6)Ta(2)O(9+x) (SBT) thin films with a STO seeded layer on MIM structure showed prefer (115) orientation, well crystalline and lower crystal temperature than those without STO seeded layer. The SBT thin films with STO seeded layer on MFIS structure also showed prefer (115), (006) orientation and well crystalline SBT phase annealed at 700 degrees C. The seeded layer, STO, effectively protected the evaporation of Bi through the Pt top electrode and diffusion of Bi into the Ir bottom electrode on MIM structure. It also can improve the crystallization of SBT phase, grain growth and lower crystallized temperature of SBT thin film. The memory window and leakage current densities of SBT thin films with STO seeded layers are improved significantly in comparison with those films without the STO seeded layer. In the MIM structure, the SBT thin film with STO seeded layer can decrease the leakage current density to 10-9 A/cm(2) at 100 kV/cm. In the MFIS structure, the SBT thin film with STO seeded layer also can improve the memory window and lead to lower leakage current at low voltage.en_US
dc.language.isoen_USen_US
dc.titleCharacteristics of SrTiO(3) Insulated Layer in SBT Ferroelectric Thin Filmsen_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.doi10.1080/00150190902869913en_US
dc.identifier.journalFERROELECTRICSen_US
dc.citation.volume382en_US
dc.citation.issueen_US
dc.citation.spage92en_US
dc.citation.epage99en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
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