電極/鐵電薄膜/結緣層/半導體結構之製程與電特性劣化研究(II)

Title:	電極/鐵電薄膜/結緣層/半導體結構之製程與電特性劣化研究(II) Processing and Characteristic Degradation of Metal-Ferroelectric-Insulator-Semiconductor (II)
Authors:	陳三元 CHEN SAN-YUAN 交通大學材料科學與工程系
Issue Date:	2002
Gov't Doc #:	NSC91-2215-E009-051
URI:	http://hdl.handle.net/11536/93066 https://www.grb.gov.tw/search/planDetail?id=784427&docId=150777
Appears in Collections:	Research Plans

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APA	陳., & CHEN S. (2002). 電極/鐵電薄膜/結緣層/半導體結構之製程與電特性劣化研究(II). https://www.grb.gov.tw/search/planDetail?id=784427&docId=150777.
Bibtex	@article{2002, title={電極/鐵電薄膜/結緣層/半導體結構之製程與電特性劣化研究(II)}, author={陳三元 and CHEN SAN-YUAN}, journal={https://www.grb.gov.tw/search/planDetail?id=784427&docId=150777}, year={2002}, url={https://ir.lib.nycu.edu.tw/handle/11536/93066}, }