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dc.contributor.authorLuo, Wun-Chengen_US
dc.contributor.authorLin, Kuan-Liangen_US
dc.contributor.authorHuang, Jiun-Jiaen_US
dc.contributor.authorLee, Chung-Lunen_US
dc.contributor.authorHou, Tuo-Hungen_US
dc.date.accessioned2014-12-08T15:22:46Z-
dc.date.available2014-12-08T15:22:46Z-
dc.date.issued2012-04-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://hdl.handle.net/11536/16087-
dc.description.abstractThis letter proposes a novel technique for predicting with high confidence the disturbance of the resistive-switching random access memory (RRAM) RESET state based on ramped voltage stress. The technique yields statistical distributions and voltage acceleration parameters equivalent to those of a conventional constant voltage method. Several ramp rates and acceleration models were validated for the accuracy regarding conversion between the two methods. The proposed method not only reduces the time and cost of reliability analysis but also provides a quantitative link between disturbance properties and the widely available RRAM data measured by a linear voltage ramp. Additionally, the non-Poisson area scaling supports the localized filament model.en_US
dc.language.isoen_USen_US
dc.subjectRead disturben_US
dc.subjectreliabilityen_US
dc.subjectresistive switchingen_US
dc.subjectresistive-switching random access memory (RRAM)en_US
dc.subjectvoltage acceleration modelen_US
dc.titleRapid Prediction of RRAM RESET-State Disturb by Ramped Voltage Stressen_US
dc.typeArticleen_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume33en_US
dc.citation.issue4en_US
dc.citation.epage597en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000302232900044-
dc.citation.woscount8-
Appears in Collections:Articles


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