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dc.contributor.authorChien, Ching-Yenen_US
dc.contributor.authorHuang, Sheng-Chiehen_US
dc.contributor.authorPan, Chia-Hoen_US
dc.contributor.authorFang, Ce-Minen_US
dc.contributor.authorChen, Liang-Geeen_US
dc.date.accessioned2014-12-08T15:23:46Z-
dc.date.available2014-12-08T15:23:46Z-
dc.date.issued2009en_US
dc.identifier.isbn978-1-4244-2975-2en_US
dc.identifier.urihttp://hdl.handle.net/11536/16585-
dc.description.abstractWith rapid progress of sensors, display devices, and computing engines, image application exists everywhere. High quality, high compression rates of digital image and low computational cost are important factors of consumer electronics. In this paper, we proposed a 4:4:4 lossless JPEG XR encoder design. In JPEG XR encoder, entropy coding is a critical module of encoder. We proposed a well-defined timing schedule of pipeline architecture to speed up the entropy encoding, which is the most computationally intensive part in JPEG XR encoder. This design can be used for the digital photography applications to achieve the low complexity of computation, low storage, and high dynamic range.en_US
dc.language.isoen_USen_US
dc.subjectJPEG XRen_US
dc.subjectHD-Photoen_US
dc.subjectencoderen_US
dc.subjectASICen_US
dc.titlePipelined Arithmetic Encoder Design for Lossless JPEG XR Encoderen_US
dc.typeProceedings Paperen_US
dc.identifier.journalISCE: 2009 IEEE 13TH INTERNATIONAL SYMPOSIUM ON CONSUMER ELECTRONICS, VOLS 1 AND 2en_US
dc.citation.spage859en_US
dc.citation.epage862en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000273282100222-
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