Full metadata record
DC FieldValueLanguage
dc.contributor.authorHung, Jui-Huien_US
dc.contributor.authorChen, Sau-Geeen_US
dc.date.accessioned2014-12-08T15:03:04Z-
dc.date.available2014-12-08T15:03:04Z-
dc.date.issued2008en_US
dc.identifier.isbn978-4-8855-2232-1en_US
dc.identifier.urihttp://hdl.handle.net/11536/1663-
dc.description.abstractThis work presents a high-performance bit-flipping (BF) algorithm utilizing a proposed syndrome vote technique of a defined culprit bit set, named CVBF algorithm for LDPC decoding. It can achieve significant decoding performance improvements by about 0.9dB over the most efficient BF algorithm, owing to the introduced an additional syndrome vote procedure after updating the flipping reliabilities of all the received bits in each iteration. Moreover, its performance is comparable to the min-sum algorithm (MSA) under the condition of same iteration number, but with much lower complexity per iteration. The proposed syndrome vote scheme only costs little overhead in hardware realization. Besides, an early termination strategy suited for the proposed algorithm is also devised to further reduce the iteration number.en_US
dc.language.isoen_USen_US
dc.subjectChannel codingen_US
dc.subjectLDPC codeen_US
dc.subjectbit flipping algorithmen_US
dc.titleAn Efficient BF LDPC Decoding Algorithm Based on A Syndrome Vote Schemeen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2008 14TH ASIA-PACIFIC CONFERENCE ON COMMUNICATIONS, (APCC), VOLS 1 AND 2en_US
dc.citation.spage673en_US
dc.citation.epage677en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000269939900141-
Appears in Collections:Conferences Paper