完整後設資料紀錄
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dc.contributor.authorSu, Man-Yunen_US
dc.contributor.authorShih, Che-Huaen_US
dc.contributor.authorHuang, Juinn-Daren_US
dc.contributor.authorJou, Jing-Yangen_US
dc.date.accessioned2014-12-08T15:24:37Z-
dc.date.available2014-12-08T15:24:37Z-
dc.date.issued2006en_US
dc.identifier.isbn0-7803-9451-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/17088-
dc.description.abstractInterface compliance verification plays a very important role in modern SoC designs. In order to perform a quantitative analysis of simulation completeness, adequate coverage metrics are mandatory. In this paper, we propose a finite state machine (FSM) based transaction-level functional coverage methodology for interface compliance verification. A language, State-Oriented Language (SOL), is developed to specify functional transactions mainly at the higher FSM level instead of lower logic or signal level. By utilizing SOL, it is simple and rigorous to specify interesting transactions from the specification FSM of the target interface protocol. Experimental results show that the proposed methodology can effectively improve the verification quality as well as increase the efficiency of regression verification.en_US
dc.language.isoen_USen_US
dc.titleFSM-based transaction-level functional coverage for interface compliance verificationen_US
dc.typeProceedings Paperen_US
dc.identifier.journalASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGSen_US
dc.citation.spage448en_US
dc.citation.epage453en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000237227500091-
顯示於類別:會議論文