Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yen, Shao-Wei | en_US |
dc.contributor.author | Hu, Ming-Chih | en_US |
dc.contributor.author | Chen, Chih-Lung | en_US |
dc.contributor.author | Chang, Hsie-Chia | en_US |
dc.contributor.author | Jou, Shyh-Jye | en_US |
dc.contributor.author | Lee, Chen-Yi | en_US |
dc.date.accessioned | 2014-12-08T15:24:38Z | - |
dc.date.available | 2014-12-08T15:24:38Z | - |
dc.date.issued | 2009 | en_US |
dc.identifier.isbn | 978-1-4244-4072-6 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17096 | - |
dc.description.abstract | An area-efficient and fully-compliant decoder for convolutional turbo code (CTC) of WiMAX 802.16e is presented. The proposed decoder can support all 17 modes specified in IEEE 802.16e system. By scaling the extrinsic information, the Max-Log MAP algorithm is used to reduce the hardware complexity with the minimized performance loss. A two-phase extrinsic memory and reversed sliding window technique are demonstrated for less memory requirement and decoding latency. Moreover, a division-free reconfigurable interleaver architecture is implemented by simple addition and subtraction instead of division. Fabricated with the 90nm CMOS process, the proposed CTC decoder chip which occupies core area of 0.92mm(2) can achieve 30Mb/s with 23.4mW power consumption. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A 0.92mm(2) 23.4mW Fully-Compliant CTC Decoder for WiMAX 802.16e Application | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | PROCEEDINGS OF THE IEEE 2009 CUSTOM INTEGRATED CIRCUITS CONFERENCE | en_US |
dc.citation.spage | 191 | en_US |
dc.citation.epage | 194 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000275926300041 | - |
Appears in Collections: | Conferences Paper |