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dc.contributor.authorYen, Shao-Weien_US
dc.contributor.authorHu, Ming-Chihen_US
dc.contributor.authorChen, Chih-Lungen_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.contributor.authorJou, Shyh-Jyeen_US
dc.contributor.authorLee, Chen-Yien_US
dc.date.accessioned2014-12-08T15:24:38Z-
dc.date.available2014-12-08T15:24:38Z-
dc.date.issued2009en_US
dc.identifier.isbn978-1-4244-4072-6en_US
dc.identifier.urihttp://hdl.handle.net/11536/17096-
dc.description.abstractAn area-efficient and fully-compliant decoder for convolutional turbo code (CTC) of WiMAX 802.16e is presented. The proposed decoder can support all 17 modes specified in IEEE 802.16e system. By scaling the extrinsic information, the Max-Log MAP algorithm is used to reduce the hardware complexity with the minimized performance loss. A two-phase extrinsic memory and reversed sliding window technique are demonstrated for less memory requirement and decoding latency. Moreover, a division-free reconfigurable interleaver architecture is implemented by simple addition and subtraction instead of division. Fabricated with the 90nm CMOS process, the proposed CTC decoder chip which occupies core area of 0.92mm(2) can achieve 30Mb/s with 23.4mW power consumption.en_US
dc.language.isoen_USen_US
dc.titleA 0.92mm(2) 23.4mW Fully-Compliant CTC Decoder for WiMAX 802.16e Applicationen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE IEEE 2009 CUSTOM INTEGRATED CIRCUITS CONFERENCEen_US
dc.citation.spage191en_US
dc.citation.epage194en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000275926300041-
Appears in Collections:Conferences Paper