標題: | An LDPC decoder chip based on self-routing network for IEEE 802.16e applications |
作者: | Liu, Chih-Hao Yen, Shau-Wei Chen, Chih-Lung Chang, Hsie-Chia Lee, Chen-Yi Hsu, Yar-Sun Jou, Shyh-Jye 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | decoder architectures;IEEE 802.16;iterative decoders;LDPC codes;phase-overlapping;self-routing;WiMax |
公開日期: | 1-三月-2008 |
摘要: | An LDPC decoder chip fully compliant to IEEE 802.16e applications is presented. Since the parity check matrix can be decomposed into sub-matrices which are either a zero-matrix or a cyclic shifted matrix, a phase-overlapping message passing scheme is applied to update messages immediately, leading to enhance decoding throughput. With only one shifter-based permutation structure, a self-routing switch network is proposed to merge 19 different sub-matrix sizes as defined in IEEE 802.16e and enable parallel message to be routed without congestion. Fabricated in the 90 nm 1P9M CMOS process, this chip achieves 105 Mb/s at 20 iterations while decoding the rate-5/6 2304-bit code at 150 MHz operation frequency. To meet the maximum data rate in IEEE 802.16e, this chip operates at 109 MHz frequency and dissipates 186 mW at 1.0 V supply. |
URI: | http://dx.doi.org/10.1109/JSSC.2007.916610 http://hdl.handle.net/11536/9608 |
ISSN: | 0018-9200 |
DOI: | 10.1109/JSSC.2007.916610 |
期刊: | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Volume: | 43 |
Issue: | 3 |
起始頁: | 684 |
結束頁: | 694 |
顯示於類別: | 期刊論文 |