標題: Design of 2xVDD-Tolerant I/O Buffer with 1xVDD CMOS Devices
作者: Ker, Ming-Dou
Lin, Yan-Liang
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2009
摘要: A new 2xVDD-tolerant I/O buffer realized with only 1xVDD devices has been proposed and verified in a 0.18-mu m CMOS process. With the dynamic source output technique and the new gate-controlled circuit, the new proposed I/O buffer can transmit and receive the signals with the voltage swing twice as high as the normal power supply voltage (VDD) without suffering gate-oxide reliability problem. The proposed 2xVDD-tolerant I/O circuit solution can be implemented in different nanoscale CMOS processes to meet the mixed-voltage interface applications in microelectronic systems.
URI: http://hdl.handle.net/11536/17129
ISBN: 978-1-4244-4072-6
期刊: PROCEEDINGS OF THE IEEE 2009 CUSTOM INTEGRATED CIRCUITS CONFERENCE
起始頁: 539
結束頁: 542
顯示於類別:會議論文