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dc.contributor.authorHong, Hao-Chiaoen_US
dc.contributor.authorLiang, Sheng-Chuanen_US
dc.date.accessioned2014-12-08T15:24:42Z-
dc.date.available2014-12-08T15:24:42Z-
dc.date.issued2006en_US
dc.identifier.isbn978-0-7695-2628-7en_US
dc.identifier.issn1081-7735en_US
dc.identifier.urihttp://hdl.handle.net/11536/17150-
dc.description.abstractA cost effective output response analyzer (ORA) for Sigma-Delta modulation based BIST systems is presented. Instead of using Fast Fourier Transform (FFT) to derive the signal-to-noise-and-distortion ratio (SNDR) infrequency domain, the proposed ORA using the modified controlled sine wave fitting procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. It requires neither parallel multiplier nor complex CPU/DSP and bulky memory thus has a low cost. A second-order design-for-digital-testability Sigma-Delta modulator is used as the circuit under test example. Simulation results show that the SNDR differences between conventional FFT analysis and the proposed ORA have a mean and standard deviation of 0.64 dB and 0.36 dB respectively. The cost effectiveness and satisfying accuracy features make it suitable for embedded BIST applications.en_US
dc.language.isoen_USen_US
dc.titleA cost effective output response analyzer for Sigma-Delta modulation based BIST systemsen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE 15TH ASIAN TEST SYMPOSIUMen_US
dc.citation.spage255en_US
dc.citation.epage261en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000245209300045-
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