完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Hong, Hao-Chiao | en_US |
dc.contributor.author | Liang, Sheng-Chuan | en_US |
dc.date.accessioned | 2014-12-08T15:24:42Z | - |
dc.date.available | 2014-12-08T15:24:42Z | - |
dc.date.issued | 2006 | en_US |
dc.identifier.isbn | 978-0-7695-2628-7 | en_US |
dc.identifier.issn | 1081-7735 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17150 | - |
dc.description.abstract | A cost effective output response analyzer (ORA) for Sigma-Delta modulation based BIST systems is presented. Instead of using Fast Fourier Transform (FFT) to derive the signal-to-noise-and-distortion ratio (SNDR) infrequency domain, the proposed ORA using the modified controlled sine wave fitting procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. It requires neither parallel multiplier nor complex CPU/DSP and bulky memory thus has a low cost. A second-order design-for-digital-testability Sigma-Delta modulator is used as the circuit under test example. Simulation results show that the SNDR differences between conventional FFT analysis and the proposed ORA have a mean and standard deviation of 0.64 dB and 0.36 dB respectively. The cost effectiveness and satisfying accuracy features make it suitable for embedded BIST applications. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A cost effective output response analyzer for Sigma-Delta modulation based BIST systems | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | PROCEEDINGS OF THE 15TH ASIAN TEST SYMPOSIUM | en_US |
dc.citation.spage | 255 | en_US |
dc.citation.epage | 261 | en_US |
dc.contributor.department | 電控工程研究所 | zh_TW |
dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
dc.identifier.wosnumber | WOS:000245209300045 | - |
顯示於類別: | 會議論文 |