完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Kuo, Yu-Ting | en_US |
dc.contributor.author | Lin, Tay-Jyi | en_US |
dc.contributor.author | Cho, Yi | en_US |
dc.contributor.author | Liu, Chih-Wei | en_US |
dc.contributor.author | Jen, Chein-Wei | en_US |
dc.date.accessioned | 2014-12-08T15:24:49Z | - |
dc.date.available | 2014-12-08T15:24:49Z | - |
dc.date.issued | 2006 | en_US |
dc.identifier.isbn | 978-0-7803-9389-9 | en_US |
dc.identifier.issn | 0271-4302 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17259 | - |
dc.description.abstract | This paper presents a programmable FIR core with a compact adder-based computing engine and an automatic code generator. The FIR core saves 50% area of 'conventional MAC-based cores in the 0.13 mu m implementation. Besides, the complexity-aware code generator synthesizes optimized FIR programs for a user-defined sampling period. It explores an optimal scaling factor with common subexpression elimination automatically. In our simulations, the proposed approach reduces about 10%similar to 18% computing time of MAC-based FIR cores with comparable filtering performance. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Programmable FIR filter with adder-based computing engine | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS | en_US |
dc.citation.spage | 1756 | en_US |
dc.citation.epage | 1759 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000245413502046 | - |
顯示於類別: | 會議論文 |