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dc.contributor.authorKuo, Yu-Tingen_US
dc.contributor.authorLin, Tay-Jyien_US
dc.contributor.authorCho, Yien_US
dc.contributor.authorLiu, Chih-Weien_US
dc.contributor.authorJen, Chein-Weien_US
dc.date.accessioned2014-12-08T15:24:49Z-
dc.date.available2014-12-08T15:24:49Z-
dc.date.issued2006en_US
dc.identifier.isbn978-0-7803-9389-9en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/17259-
dc.description.abstractThis paper presents a programmable FIR core with a compact adder-based computing engine and an automatic code generator. The FIR core saves 50% area of 'conventional MAC-based cores in the 0.13 mu m implementation. Besides, the complexity-aware code generator synthesizes optimized FIR programs for a user-defined sampling period. It explores an optimal scaling factor with common subexpression elimination automatically. In our simulations, the proposed approach reduces about 10%similar to 18% computing time of MAC-based FIR cores with comparable filtering performance.en_US
dc.language.isoen_USen_US
dc.titleProgrammable FIR filter with adder-based computing engineen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGSen_US
dc.citation.spage1756en_US
dc.citation.epage1759en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000245413502046-
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