The Design of Low-Power CIFF Structure Second-Order Sigma-Delta Modulator

doi:10.1109/MWSCAS.2009.5236077

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DC Field	Value	Language
dc.contributor.author	Su, Pin-Han	en_US
dc.contributor.author	Chiueh, Herming	en_US
dc.date.accessioned	2014-12-08T15:24:56Z	-
dc.date.available	2014-12-08T15:24:56Z	-
dc.date.issued	2009	en_US
dc.identifier.isbn	978-1-4244-4479-3	en_US
dc.identifier.issn	1548-3746	en_US
dc.identifier.uri	http://hdl.handle.net/11536/17306	-
dc.identifier.uri	http://dx.doi.org/10.1109/MWSCAS.2009.5236077	en_US
dc.description.abstract	This paper presents the design and implementation of a low power sigma-delta modulator (SDM) with a standard 0.18-mu m CMOS technology. A current optimization technique is utilized in proposed design to reduce the power of operational trans-conductance amplifier(OTA). Using a chain of Integrators with weighted feed-forward summation (CIFF) structure and optimized single-stage class-A OTA with positive feedback to minimize the power consumption, the second-order SDM achieves a SNR of 64dB that be able to process the signal form DC to 16 KHz. The power consumption is only 18.1 uW from a 1-V supply.	en_US
dc.language.iso	en_US	en_US
dc.title	The Design of Low-Power CIFF Structure Second-Order Sigma-Delta Modulator	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.doi	10.1109/MWSCAS.2009.5236077	en_US
dc.identifier.journal	2009 52ND IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2	en_US
dc.citation.spage	377	en_US
dc.citation.epage	380	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000277574000092	-
Appears in Collections:	Conferences Paper

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