Design of a 125 mu W, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Liu, Tsu-Ming	en_US
dc.contributor.author	Chung, Ching-Che	en_US
dc.contributor.author	Lee, Chen-Yi	en_US
dc.contributor.author	Lin, Ting-An	en_US
dc.contributor.author	Wang, Sheng-Zen	en_US
dc.date.accessioned	2014-12-08T15:24:57Z	-
dc.date.available	2014-12-08T15:24:57Z	-
dc.date.issued	2006	en_US
dc.identifier.isbn	1-59593-381-6	en_US
dc.identifier.issn	0738-100X	en_US
dc.identifier.uri	http://hdl.handle.net/11536/17331	-
dc.description.abstract	A design of MPEG-2 and H.264/AVC video decoder is demonstrated in a 0.18 mu m CMOS [1]. The key design issues involved in this advanced IC are discussed, including improving area and power efficiency. Power dissipation is greatly lowered through the architectural exploration. Measurement results show that MPEG-2 and H.264/AVC real-time decoding of QCIF@15fps are achieved at 1.15MHz with power dissipation of 108 mu W and 125 mu W respectively at 1V supply voltage.	en_US
dc.language.iso	en_US	en_US
dc.subject	design	en_US
dc.subject	measurement	en_US
dc.subject	performance	en_US
dc.subject	MPEG-2	en_US
dc.subject	H.264/AVC	en_US
dc.subject	mobile	en_US
dc.subject	low-power	en_US
dc.title	Design of a 125 mu W, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	43rd Design Automation Conference, Proceedings 2006	en_US
dc.citation.spage	288	en_US
dc.citation.epage	289	en_US
dc.contributor.department	交大名義發表	zh_TW
dc.contributor.department	National Chiao Tung University	en_US
dc.identifier.wosnumber	WOS:000240104100057	-
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