完整後設資料紀錄
DC 欄位語言
dc.contributor.authorKer, Ming-Douen_US
dc.date.accessioned2014-12-08T15:24:57Z-
dc.date.available2014-12-08T15:24:57Z-
dc.date.issued2006en_US
dc.identifier.isbn1-4244-0460-6en_US
dc.identifier.urihttp://hdl.handle.net/11536/17334-
dc.description.abstractIn this tutorial, we teach useful on-chip ESD protection designs for CMOS integrated circuits. The contents include (1) Introduction to Electrostatic Discharge, (2) Design Techniques of ESD Protection Circuit, (3) Whole-Chip ESD Protection Design, and (4) ESD Protection for Mixed-Voltage I/O Interface. The clear ESD protection design concepts and detailed circuit implementations are presented in this course. ESD protection design is more important in the nanoscale CMOS technology. High ESD robustness can not be achieved with only process solutions. The circuit design solutions should be added into the chips with suitable layout arrangement to achieve the purpose of whole-chip ESD protection for IC products.en_US
dc.language.isoen_USen_US
dc.titleESD (Electrostatic Discharge) protection design for nanoelectronics in CMOS technologyen_US
dc.typeProceedings Paperen_US
dc.identifier.journalAdvanced Signal Processing, Circuits, and System Design Techniques for Communicationsen_US
dc.citation.spage217en_US
dc.citation.epage279en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000239524300006-
顯示於類別:會議論文