完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lin, Fang-Ju | en_US |
dc.contributor.author | Chiueh, Herming | en_US |
dc.date.accessioned | 2014-12-08T15:25:03Z | - |
dc.date.available | 2014-12-08T15:25:03Z | - |
dc.date.issued | 2006 | en_US |
dc.identifier.isbn | 978-1-4244-0394-3 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17422 | - |
dc.identifier.uri | http://dx.doi.org/10.1109/ICECS.2006.379902 | en_US |
dc.description.abstract | Recent research has proposed using stream processors for media applications. Since a programmable Stream Processor could utilize various hardware micro-architectures for diverse media applications, decision on a suitable micro-architectures to achieve efficiencies and hardware cost is critical. In this paper, a micro-architecture simulator for stream processor is implemented. The simulator evaluate the performance of media application executed on various micro-architectures, and then to analyze the utility rate of hardware and consumption of memory. By comparing the performance of media application executed on diverse micro-architectures, the optimized hardware micro-architecture can be determined for specific application and suitable micro-architecture of Stream Processor can be implemented on later VLSI for different targeting systems. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A micro-architecture simulator for multimedia stream processor | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.doi | 10.1109/ICECS.2006.379902 | en_US |
dc.identifier.journal | 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3 | en_US |
dc.citation.spage | 768 | en_US |
dc.citation.epage | 771 | en_US |
dc.contributor.department | 電信工程研究所 | zh_TW |
dc.contributor.department | Institute of Communications Engineering | en_US |
dc.identifier.wosnumber | WOS:000252489600192 | - |
顯示於類別: | 會議論文 |