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dc.contributor.authorLin, Chia-Chunen_US
dc.contributor.authorLin, Yu-Kunen_US
dc.contributor.authorChang, Tian-Sheuanen_US
dc.date.accessioned2014-12-08T15:25:05Z-
dc.date.available2014-12-08T15:25:05Z-
dc.date.issued2006en_US
dc.identifier.isbn978-1-4244-0386-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/17460-
dc.description.abstractThe paper presents a hardware friendly fast algorithm and its architecture for motion estimation (ME) in H.264 video coding. The fast algorithm adopts the quarter pel subsampling and mode filtering that reduces the computing complexity of integer ME by 75%, and only two modes instead of various modes are refined for fractional ME. This also can save about 80% fractional ME cycle counts in average. The simulation result shows that it only increases the bit rate within 2% and at most 0.14dB quality degradation. Finally, the resulted parallel architecture only costs 58% of area cost and requires 48% of cycle counts when compared with the previous designs.en_US
dc.language.isoen_USen_US
dc.titleA fast algorithm and its architecture for motion estimation in MPEG-4 AVC/H.264 video codingen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2006 IEEE Asia Pacific Conference on Circuits and Systemsen_US
dc.citation.spage1248en_US
dc.citation.epage1251en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000246793200312-
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