標題: VLSI architecture design of motion estimator and in-loop filter for MPEG-4 AVC/H.264 encoders
作者: Wang, YY
Peng, YT
Tsai, CJ
資訊工程學系
Department of Computer Science
公開日期: 2004
摘要: In this paper, a new complexity-reduced method and its hardware architecture for motion estimation and the in-loop filter for MPEG-4 AVC/H.264 is proposed. The feature of the proposed method is focused on the computation reduction for the motion search algorithm among multiple reference frames and the mode partition determination. Furthermore, to verify the functionality and performance of the proposed hardware design, an emulation board platform, the ARM Integrator, is used for H.264 hardware/software co-development. The experimental results show that the proposed method has excellent performance with little or no degradation of coding efficiency.
URI: http://hdl.handle.net/11536/18393
期刊: 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS
起始頁: 149
結束頁: 152
顯示於類別:會議論文