標題: A low-power reconfigurable mixed-radix FFT/IFFT processor
作者: Lai, Chi-Chen
Hwang, Wei
友訊交大聯合研發中心
D Link NCTU Joint Res Ctr
公開日期: 2006
摘要: In this paper, we present a novel FFT/IFFT processor, called reconfigurable mixed-radix (RMR) FFT. It can be easily reconfigured as from 16-point to 4096-point FFT/IFFT with proper mixed-radix algorithm assigned for each mode. The proposed processor is characterized with scalable power-consumption for different FFT/IFFT sizes. Unlike the general pipeline-based architectures which use a larger internal wordlength to achieve a high signal to noise ratio (SNR), our processor keeps the internal wordlength the same as the wordlength of the input data while adopting the block-floating point (BFP) approach to maintain the SNR.
URI: http://hdl.handle.net/11536/17465
ISBN: 978-1-4244-0386-8
期刊: 2006 IEEE Asia Pacific Conference on Circuits and Systems
起始頁: 1931
結束頁: 1934
Appears in Collections:Conferences Paper