A low-power reconfigurable mixed-radix FFT/IFFT processor

Abstract

In this paper, we present a novel FFT/IFFT processor, called reconfigurable mixed-radix (RMR) FFT. It can be easily reconfigured as from 16-point to 4096-point FFT/IFFT with proper mixed-radix algorithm assigned for each mode. The proposed processor is characterized with scalable power-consumption for different FFT/IFFT sizes. Unlike the general pipeline-based architectures which use a larger internal wordlength to achieve a high signal to noise ratio (SNR), our processor keeps the internal wordlength the same as the wordlength of the input data while adopting the block-floating point (BFP) approach to maintain the SNR.