ESC robustness of 40-V CMOS devices with/without drift implant

doi:10.1109/IRWS.2006.305237

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chang, Wei-Jen	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.contributor.author	Lai, Tai-Hsiang	en_US
dc.contributor.author	Tang, Tien-Hao	en_US
dc.contributor.author	Su, Kuan-Cheng	en_US
dc.date.accessioned	2014-12-08T15:25:06Z	-
dc.date.available	2014-12-08T15:25:06Z	-
dc.date.issued	2006	en_US
dc.identifier.isbn	978-1-4244-0296-0	en_US
dc.identifier.issn	1930-8841	en_US
dc.identifier.uri	http://hdl.handle.net/11536/17476	-
dc.identifier.uri	http://dx.doi.org/10.1109/IRWS.2006.305237	en_US
dc.description.abstract	The dependences of device structures and layout parameters on ESD robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the high-voltage (HV) MOSFETs without drift implant in the drain region have better TLP-measured It2 and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased.	en_US
dc.language.iso	en_US	en_US
dc.title	ESC robustness of 40-V CMOS devices with/without drift implant	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.doi	10.1109/IRWS.2006.305237	en_US
dc.identifier.journal	2006 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP, FINAL REPORT	en_US
dc.citation.spage	167	en_US
dc.citation.epage	170	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000245236100039	-
顯示於類別：	會議論文

文件中的檔案：

000245236100039.pdf

若為 zip 檔案，請下載檔案解壓縮後，用瀏覽器開啟資料夾中的 index.html 瀏覽全文。