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dc.contributor.authorChang, Wei-Jenen_US
dc.contributor.authorKer, Ming-Douen_US
dc.contributor.authorLai, Tai-Hsiangen_US
dc.contributor.authorTang, Tien-Haoen_US
dc.contributor.authorSu, Kuan-Chengen_US
dc.date.accessioned2014-12-08T15:25:06Z-
dc.date.available2014-12-08T15:25:06Z-
dc.date.issued2006en_US
dc.identifier.isbn978-1-4244-0296-0en_US
dc.identifier.issn1930-8841en_US
dc.identifier.urihttp://hdl.handle.net/11536/17476-
dc.identifier.urihttp://dx.doi.org/10.1109/IRWS.2006.305237en_US
dc.description.abstractThe dependences of device structures and layout parameters on ESD robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the high-voltage (HV) MOSFETs without drift implant in the drain region have better TLP-measured It2 and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased.en_US
dc.language.isoen_USen_US
dc.titleESC robustness of 40-V CMOS devices with/without drift implanten_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/IRWS.2006.305237en_US
dc.identifier.journal2006 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP, FINAL REPORTen_US
dc.citation.spage167en_US
dc.citation.epage170en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000245236100039-
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